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GPS Receiver RF Front End IC
Preliminary
PT9120
DESCRIPTION
The PT9120 is a single chip Global Positioning System (GPS) receiver front-end IC requiring few external components and offering extremely low power consumption. The PT9120 employs a super-heterodyne receiver topology which down-converts the 1575.42MHz L1-band GPS signal to a 1st IF. The 1st IF is then filtered by an off-chip L-C filter and subsequently sub-sampled by the 2-bit A/D converter to provide both sign and magnitude quantized CMOS level outputs to base band inputs.
FEATURES
* * * * * * * * GPS L1-band (C/A code) receiver Integrated LNA and antenna detector Fully-monolithic VCO Support for several reference frequencies 2-bit ADC output (sign and magnitude) Extremely low current consumption (7mA at AVDD=TVDD=2.5V) Multiple power-down modes Available in 28 pins or 24 pins, QFN package
APPLICATION
* GPS systems
PT9120 PRE1.0
-1-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
BLOCK DIAGRAM
PT9120 PRE1.0
-2-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
PIN CONFIGURATION
28-PIN, QFN
PT9120 PRE1.0
-3-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
24-PIN, QFN
PT9120 PRE1.0
-4-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
PIN DESCRIPTION
Pin Name I/O SGN MAG AOK CP TVSS TVDD XEN XI XO VB PLL AON LNI ISNS PVDD LNO AVDD AVSS RFIN VBG IF1P IF1N IF2P IF2N MODE AGCCAP P1 P0 O O Description Quantized 2nd IF "sign" bit Quantized 2nd IF "magnitude" bit Active antenna status output (AOK = HIGH = active antenna OK; O AOK=LOW=active antenna either open or shorted) I/O Reference clock input/output G Ground (digital circuitry) P Supply voltage (digital circuitry) Crystal oscillator enable pin I (XEN=HIGH=enabled; XEN=LOW=disabled) I Crystal oscillator input O Crystal oscillator output O Regulator (1.9V) output O Charge pump output O Antenna switch-controlled supply voltage to active antenna I LNA input I Antenna detector current sense input O Supply voltage (active antenna) O LNA output P Supply voltage (analog circuitry) G Ground (analog circuitry) I Mixer input O Band gap reference (1.23V) output O Differential mixer IF output/differential first-stage IF amplifier O input I Differential first-stage IF amplifier output/differential IF AGC I input I Reference frequency mode select input I/O AGC capacitor connection. Sets the AGC time constant. I Power-down control pins (see PT9120 operating modes) I Pin No. 28-pin 24-pin 1 1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -
PT9120 PRE1.0
-5-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
FUNCTION DESCRIPTION
The PT9120 low power GPS receiver IC employs a double-conversion, super-heterodyne receiver topology to achieve excellent performance. A complete GPS L1-band receiver front-end may be constructed using the PT9120 IC together with an active antenna, RF and IF filters, and a reference crystal. The PT9120 consists of an RF LNA; an RF mixer; complete frequency synthesizer including a VCO, phase/frequency detector (PFD), charge pump, input and reference dividers, and a reference crystal oscillator; IF AGC amplifier; and a 2-bit A/D converter with CMOS-level outputs. The PT9120 includes an on-chip voltage regulator and an integrated antenna detector and switch capable of supplying power to an active antenna as well as providing current limiting protection when an antenna open or short has been detected. The on-chip voltage regulator provides a stable 1.9V output at the VB pin. In addition, the PT9120 implements four distinct operating modes including two low power modes and one complete power-down mode. The application circuit includes the PT9120 IC and provides an option for either a patch antenna or active antenna, a single connector to a power supply, power-down control inputs, and digital data outputs. Among the various external parts are an external LNA, filter and oscillator components (TCXO), de-coupling resistors and capacitors for the analog and digital power supplies, and the SAW filter between the discrete LNA output and the PT9120 RF input.
ANTENNA DETECTOR/SWITCH
The PT9120 integrates an antenna detector and switch to supply power to and control an optional active antenna. The supply voltage for an active antenna is applied to the PT9120's PVDD pin. The actual voltage supply connection to the antenna is available on the AON pin. An external resistor between PVDD and ISNS is used to set the "antenna short" and "antenna open" current thresholds. The actual antenna current is derived from the measured voltage drop across the external sense resistor. The minimum and maximum voltage drop thresholds are internally set to 36mV and 300mV, respectively. For a 56 external sense resistor, these voltage drops correspond to minimum ("antenna open") and maximum ("antenna short") current thresholds Imin = 36mV/56 = 640A and Imax = 300mV/56 = 5.35mA. Once the PT9120 is set to the fully active mode, internal antenna detector circuitry determines whether an active antenna is properly connected by monitoring the current consumed by the antenna. As long as the monitored current falls within the range delineated by Imin and Imax, the AOK pin is set to logic HIGH, and an internal switch within the PT9120 is closed to allow voltage to be supplied to the antenna from the AON pin. Otherwise, the AOK pin is set to logic LOW, and additionally, if the voltage drop across the sense resistor is > 300mV, the output current thru the AON pin is limited to a value around 10% above Imax.
PT9120 PRE1.0
-6-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
If desired, the antenna switch may be bypassed by connecting the active antenna directly to the ISNS pin. Furthermore, the antenna detector may be bypassed by shorting PVDD to ISNS (AOK will always be set to logic LOW). In both these cases, the short circuit current-limiting protection circuit is disabled. If no active antenna is used, PVDD must be connected to ground, while AON and ISNS may be connected to ground or left open. In this case, the AOK pin will always be set to logic HIGH when the PT9120 is in fully active mode, and will be set to logic LOW in all other modes.
EXTERNAL LNA
As shown in the application circuit, an off-chip cascade LNA (15dB gain and 1.5dB NF) may be used to amplify the 1575.42MHz L1 GPS RF input signal prior to sending it to the RF input of the PT9120. The input and output impedances for the LNA are nominally 50 at 1575.42MHz.
RF LNA
Impedance matching at the PT9120's integrated LNA's input and output is required. At the LNA input, an optimum noise match is required for best sensitivity performance. At the LNA output, a match to the 50 impedance of the SAW filter is required. Typical matching topologies and component values are shown in Typical PT9120 RF application circuit schematic. Note that the layout of the application PCB may affect these component values.
RF MIXER
The RF mixer down-converts the GPS signal band to a 1st IF near 20MHz (depending upon the chosen crystal reference frequency as specified in Supported frequency plans). The RFIN input of the mixer is on-chip matched to 50 and is internally biased near ground potential (AVSS) and should not receive any external dc biasing.
IF FILTER AND AGC
The PT9120 also requires 2 external IF filters at the mixer output for channel selection and to reject image frequency noise at the input of the sub-sampling 2-bit A/D converter. These filters should have a bandwidth of at least 2MHz, centered at the 1st IF corresponding to the frequency plan chosen (see Supported frequency plans), and should also provide a low impedance path to ground at the local oscillator frequency. A typical GPS receiver application may include the 4th order L-C band-pass filter connected between the IF1P/IF1N and IF2P/IF2N pins as shown in the application circuit of Typical PT9120 RF application circuit schematic. With the component values shown, the filter is centered at 20.46MHz and has a bandwidth of roughly 4MHz to accommodate component tolerances of 5%. On the PCB, the IF filter components should be placed far away from digital signals.
PT9120 PRE1.0
-7-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
The IF- amplifier provides roughly 70dB of gain and includes 60dB of AGC range, which is sufficient to accommodate a wide range of input signals without saturation. The AGC range is 2bit output of the 2-bit A/D converter as the regulation variable and sets the gain of the 1st IF amplifier to achieve a logic HIGH duty cycle of 33% on the MAG bit output. The time constant of the AGC loop is set using a capacitor connected to the AGCCAP pin.
DIGITAL INTERFACE
The reference clock input/output pin (CP) and the 2-bit AD converter's digital output pins (SGN and MAG) are CMOS-level compatible with a low-to-high logic swing from TVSS to TVDD. The SGN and MAG outputs represent the sign and the magnitude bits, respectively, of the digitized (2-bit) 2nd IF signal. The 4 possible levels for both SGN and MAG are coded as shown in Coded SGN and MAG output signal. SGN MAG Value LOW HIGH +3 LOW LOW +1 HIGH LOW -1 HIGH HIGH -3 The SGN and MAG output bits change on the falling edge of CP and should be read in by the baseband processor on the rising edge of CP as illustrated in SGN and MAG output timing diagram.
For the PT9120, the CP pin may be used as either clock input or output. With the on-chip reference crystal oscillator enabled, the CP pin becomes an output and delivers a CMOS-level signal with a nominal duty cycle of 50% at the same frequency as the reference crystal oscillator. By disabling the on-chip crystal oscillator (setting XEN to logic LOW), the CP pin becomes an input which accepts an external CMOS-level (TVSS to TVDD) clock signal with a duty cycle between 40% and 60%.
PT9120 PRE1.0
-8-
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
The RF application circuit shown in Typical PT9120 RF application circuit schematic has been successfully interfaced with the PTC GPS base-band processor. Since the base-band processor requires a 2-bit IF input, the PT9120's SGN and MAG digital outputs are both fed to the base-band processor. Note that the SGN and MAG output pins are only capable of driving a small load, e.g. a typical digital input (2 to 4pF), and hence, they will drive neither a clock distribution tree nor a common 15pF oscilloscope probe. Overall performance degradation of the PT9120 caused by increased switching noise leading to excessive power line interference may result from high capacitive loading. This interference may be reduced by inserting series damping resistors (220 to 470) at the interface between the PT9120's SGN and MAG outputs and the base-band processor inputs. As a rule of thumb, PCB traces connected to the PT9120's digital output pins should be kept short and routed away from the external IF filter components.
CRYSTAL OSCILLATOR
The reference frequency for the PLL and the clock signal for the 2-bit A/D converter may be generated by either the on-chip crystal oscillator, or supplied externally. An external reference clock signal (such as the low amplitude signal from a typical TCXO as shown in the application circuit in Typical PT9120 RF application circuit schematic) should only be ac-coupled to the XO pin when the on-chip crystal oscillator is enabled (XEN is set to TVDD) since the on-chip oscillator device will serve as a buffer for the external signal. The external reference clock signal should have a minimum voltage swing of 400mVP-P. The on-chip crystal oscillator uses a Pierce topology and requires external crystal resonator and shunt load capacitances. The crystal oscillator is enabled by setting XEN to TVDD and disabled by setting XEN to logic LOW. The XEN pin should never be left floating. For interfacing to the PTC base-band processor, the crystal oscillator should be set to 16.368MHz.
SUPPORTED FREQUENCY PLANS
The PT9120 supports separate frequency plans for eight different reference frequencies. The selection of the reference frequency is determined by logic input level at the MODE pin (which should be hardwired to either AVDD or AVSS) and also the logic levels at the internal IC metal layer M1 and M2 pads. Supported frequency plans shows the relationship among the reference frequencies, MODE/M1/M2 logic levels, 1st and 2nd IF and LO frequencies, and N-divider divide ratios.
M1 M2 Mode Reference Frequency (MHz) 1st IF (MHz) 2nd IF (MHz) Lo Frequency (MHz) N-driver Divide Ratio
Low High High Low
Low Low High High
Low High Low High Low High Low High
16.367 13.000 (GSM) 19.800(CDMA) 19.200(CDMA) 19.680 (CDMA) 14.400(PDC) 12.600(PDC) 16.367 15.360(WCDMA)
20.55 16.58 24.42 23.25 15.55 18.18 21.87 20.55 18.94
-9-
4.188 3.58 4.62 4.051 4.127 3.78 3.328 4.188 3.58
1554.86 1592 1599.84 1552.17 1590.97 1593.6 1597.29 1554.86 1556.48
1520 1592 1616 1536 1536 1328 1648 1520 1520
August, 2007
PT9120 PRE1.0
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GPS Receiver RF Front End IC
Preliminary
PT9120
POWER-DOWN CONTROL
The PT9120 provides four distinct operating modes: (1) fully active, (2) stand-by, (3) doze, and (4) sleep. CMOS-level compatible input control pins, P1 and P0, set the operating state of the chip. The relationship between the P1 and P0 inputs and the PT9120's operating state is given in PT9120 operating modes Gray coding has been used for the P1 and P0 inputs in order to minimize glitches while switching from one operating mode to the other. When switching from doze to fully active mode, stand-by should be selected first. P1 HIGH HIGH LOW LOW P0 LOW HIGH HIGH LOW Operating Mode Fully active Stand-by Doze Sleep
POWER SUPPLY CONNECTIONS
The PT9120 minimally requires two power supply voltage connections, AVDD and TVDD. Both AVDD and TVDD which supply voltages must be well filtered, particularly the analog power supply voltage connection, AVDD. An R-C or L-C filter on the TVDD line may be used for improved noise suppression. The AVDD and TVDD supply lines must also be well de-coupled. A 100nF ceramic capacitor mounted very close to the chip package is recommended on both AVDD and TVDDTVSS. A 2.2F (or higher) tantalum capacitor may be required on AVDD, especially if AVDD is not regulated. In order to avoid switching noise interference from the digital portion of the chip, it is recommended that a star grounding topology, where AVSS and TVSS are connected at only one point very close to the chip package, be used.
PT9120 PRE1.0
- 10 -
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
ABSOLUTE MAXIMUM RATINGS
(AVSS=TVSS=VSS=0V) Parameter Supply voltage Soldering temperature Soldering time range Operating temperature Storage temperature Symbol VCC TSLD tSLD Topr Tstg Rating VSS -0.3 to VSS +4.0 255 10 -40 to 85 -55 to 125 Unit V Sec.
RECOMMEND OPERATING CONDITIONS
(AVSS=TVSS=VSS= 0V) Parameter Analog supply voltage range Digital supply voltage range Operating temperature Symbol AVDD TVDD TA Min. 2.2 1.6 -40 Rating Typ. 2.5 2.5 25 Max. 3.6 AVDD + 0.2 85 Unit V V
PT9120 PRE1.0
- 11 -
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, AVDD=TVDD=2.5V, AVSS=TVSS=0V, TA=25) Parameter Symbol Conditions Min.
DC AVDD (analog) TVDD (digital) PVDD (antenna) AVDD fully active current TVDD fully active current Sleep current (AVDD and TVDD) Antenna Detector and Switch Low trip voltage High trip voltage Maximum switch current LNA Gain Noise figure RF Mixer Conversion gain SSB noise figure IF Strip 1st IF filter voltage gain AGC amplifier maximum voltage gain AGC amplifier minimum voltage gain ADC SGN duty cycle ADC MAG duty cycle VCO frequency range VCO gain SSB phase noise Digital Interface Input logic HIGH level Input logic LOW level Output logic HIGH level Output logic LOW level Output rise time Output fall time VIH VIL VOH VOL TRISE TFALL TVDD=2.5V TVDD=2.5V TVDD=2.5V TVDD=2.5V Cload=15pF Cload=15pF 2.25 0 2 0 2.7 0.5 2.5 0.25 10 10 V V V V ns ns GVCO NFVCO 100KHz offset, 50KHz loop bandwidth setting GIFFLT GAGCH GAGCL DSGN DMAG 1.35 400 -80 550 -86 50 33 1.9 Unloaded 10 70 10 15 dB dB dB % % GHz MHz/V dBc/Hz GMIX NFMIX voltage gain, no load 16 8 17 9 18 10 dB dB
(NOTE)
Typ.
2.5
Max.
3.6 AVDD + 0.2 3.6
Unit
V V V mA A A mV
AVDD TVDD PVDD IAVDD ITVDD ISLEEP ANTVL ANTVH IPDD GLNA NFLNA PVDD = 2.2V power gain, noise matched power gain, noise matched AVDD + TVDD
2.2 1.6 2.2
6.4 350
7.0 500 1
20 12 15
36 300 400
mV mA
18 1.5
20 2.0
dB
Frequency Synthesizer (Local Oscillator)
Note: Depend on PCB layout and matching components.
PT9120 PRE1.0 - 12 August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
APPLICATION CIRCUIT
24 PINS, QFN
JP1 3 2 1
DVDD C17 1N
L9 1.5U C16 39P +5V C15 47P L8 1.2U C18 10U 1 3 U2 REGULATOR_2.8V Vin Vss CE Vout NC AVDD 5 4 C19 10N C20 1U R6 150R C21 1U DVDD
24
23
22
21
20
AGCCAP
5 4 3 2 1
SGN MAG CP GND +5V
19
JP4
U1 P1 I F2P I F2N I F1N I F1P SGN R1 10R 1 2 3 4 18 17 16 15 14 13 AVDD C14 1U
SGN MAG CP DVSS DVDD
VBG RFI AVSS AVDD LNO
MAG R2 10R CP R3 10R
DVDD JP3 3 2 1
DVDD
R4 33R C1 1U
5 6
C13 1.5P L7 4.7N
AVDD C12 470P
AON
I SNS
XEN PLL VB XI
PVDD
LNI
2
AON C11 1N
DVDD AON 10 11 12 7 8 9 4 1 X1 VDD IN TCXO OUT GND 3 2 C3 1U R7 47K C4 15P C5 100P C2 100P
PT9120_24L R5 33R AVDD PVDD C8 470P
L2 12N L1 6.8N 4 3 C6 1.5P F1 OUT GND IN GND 2 1 C7 5.6P L3 15N 1 3 C9 1N U3 OUT CAP IN GND 7 6 L4 10N C1056P
L6 33N RF_IN
SAW_FILTER
NJG1107HB3
L5 27N
PT9120 PRE1.0
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August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
28 PINS, QFN
DVDD JP1 3 2 1 JP2 3 2 1 P0 P1
+5V
1 3
U5 REGULATOR_2.5V Vin Vss CE Vout NC
5 4 C20 10N
DVDD C21 1U
+5V
1 3
U6 REGULATOR_2.8V Vin Vss CE Vout NC
5 4 C23 10N
AVDD C24 1U
2
L9 1.5U C16 1N AGC P1 P0 28 27 JP4 5 4 3 2 1 SGN MAG CP GND +5V C15 39P
26
25
24
23
22
U1 P0 P1 ACAP I F2N I F2P SGN R1 390R 1 2 3 MODE I F1N SGN IF1P 21 20 19 18 17 16 15
L8 1.2U
2 C14 47P VBG RFI C12 1.5P AVDD L7 4.7N AVDD C11 470P AVDD PVDD L2 12N L6 33N U2 OUT CAP IN GND 7 6 L4 10N C9 56P RF_IN C10 1N AON C13 1U
C19 10U
C22 10U
MAG R2 390R
MAG AOK CP DVSS DVDD AON PLL LNI XO VB XI XEN
VBG RFI AVSS AVDD LNO PVDD I SNS
JP3 3 2 1
DVDD XEN
CP C1 1U DVDD R4 33R XEN
R3 390R
4 5 6 7
PT4360 10 11 12 13 14 8 9 R5 33R XO U4 4 1 VDD IN TCXO OUT GND 3 2 PLL VB XI C17 100P XO XI C18 NC C2 1U R4 47K C3 15P C4 100P AON U3 4 3 C5 1.5P OUT GND IN GND 2 1
C8 470P
DVDD
L1 6.8N
C6 5.6P
L3 15N 1 3 C7 1N
SAW_FILTER
NJG1107HB3
L5 27N
1.2 x 1.2 cm Module
PT9120 PRE1.0
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August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
ORDER INFORMATION
Valid Part Number PT9120-QF24 (L) PT9120-QF28 (L) Package Type 24 Pins, QFN 28 Pins, QFN Top Code PT9120-QF24 PT9120-QF28
Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the date code.
PT9120 PRE1.0
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GPS Receiver RF Front End IC
Preliminary
PT9120
PACKAGE INFORMATION
24 PINS & 28 PINS, QFN
PT9120 PRE1.0
- 16 -
August, 2007
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GPS Receiver RF Front End IC
Preliminary
PT9120
24 PINS, QFN (BODY SIZE 4MM X 4MM)
Symbol A A1 A2 A3 L1 K R b D E D1 E1 D2 E2 L Min. 0.70 0 0 0.00 0 0.20 b MIN/2 0.18 Dimensions Nom. 0.75 0.02 0.55 0.20 REF. 0.25 4.00 BSC. 4.00 BSC. 0.40 Max. 0.80 0.05 0.80 0.15 14 0.30
2.20 2.20 0.30
2.60 2.60 0.50
28 PINS, QFN (BODY SIZE 5MM X 5MM)
Symbol A A1 A2 A3 L1 K R b D E D1 E1 D2 E2 L Min. 0.70 0 0 0.00 0 0.20 b MIN/2 0.18 Dimensions Nom. 0.75 0.02 0.55 0.20 REF. 0.25 5.00 BSC. 5.00 BSC. 2.70 2.70 0.55 Max. 0.80 0.05 0.80 0.15 14 0.30
2.35 2.35 0.45
3.35 3.35 0.75
PT9120 PRE1.0
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GPS Receiver RF Front End IC
Preliminary
PT9120
Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, is in degrees. 3. N is the number of the terminal positions (N=24 or 28) 4. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SPP-002, details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either A mold or marked feature. 5. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 6. Depopulation is possible in a symmetrical fashion. 7. All variations may be constructed per figure 1. Variation may alternately be constructed per figure 2 if A2, D1 & E1 are specified in the dimension tables, in all cases, the minimum "K" value of 0.20mm applies. 8. For a complete set of dimensions for each variation, see the individual variation and the common dimensions and tolerance in table. 9. Depending on the method of lead termination at the edge of the package, pull back (L1) maybe present, L minus L1 to be equal to or greater than 0.3mm. 10. When more than one variation (option) exists for the same profile height, body size (D x E), and pitch, then those variations will be denoted by an additional dash number (ie, -1, -2, etc.) designator to identify then, the new variations would be created from all or any of the following reasons lead counts ,terminal lengths, and or thermal pad sizes. 11. Refer to JEDEC MO-220, Variation WGGD-8 (for 24PIN, QFN). Refer to JEDEC MO-220, Variation WHHD-1 (for 28PIN, QFN). JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
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August, 2007

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